A resistive memory is of a metal/oxide/metal (MIM) capacitor structure. Under the action of electrical signals, the device is reversibly converted between a high resistance state (HRS) and a low resistance state (LRS) to realize a data storage function. The resistive memory has attracted great attention at home and abroad due to its excellent characteristics in terms of cell area, three-dimensional integration, low power consumption, high erasing speed, multi-value storage and the like.
There are mainly two three-dimensional integration methods for the resistive memory: one method adopts a cross array multilayer stacked structure, that is, a two-dimensional cross array structure is repeatedly fabricated and stacked in multiple layers; and the other method adopts a vertical cross array structure, in which the traditional horizontal cross array structure is rotated 90 degrees and repeatedly extended in the horizontal direction to form a three-dimensional array of a vertical structure. Compared with the multilayer stacked structure, the unit in the vertical direction of the three-dimensional array of the vertical structure is formed by filling a trench once, thus greatly saving an expensive lithography step. Although the fabrication cost of the vertical cross array structure is low, the problem that gating tubes are difficult to integrate is caused because of the absence of a patterning process for a single device, so it is the key of constructing the vertical cross array to develop a resistive device with a self-gating function.
The self-gating resistive device usually has a double-layer structure and combines a gating functional layer and a resistive functional layer. As shown in FIG. 1, it is a common practice to successively deposit a gating layer 501 and a resistive layer 601 in a trench to form an edge contact self-gating storage unit with lower electrodes 301-303 (i.e., word lines) stacked in multiple layers. By means of this method, the problem of read and write crosstalk in a vertical cross array can be solved. However, since the upper and lower word lines are connected through the gating layer, there is a problem of interlayer leakage. Because the transition voltage of the gating layer is proportional to the thickness, when the size of the array continues to shrink, the interlayer leakage phenomenon will become more prominent. Please refer to FIG. 2, which is a read/write schematic diagram of the vertical cross array. During read/write, a voltage difference V/2 (taking V/2 bias as an example) exists between upper and lower word lines. When the interlayer voltage difference approaches or exceeds the transition voltage of the gating layer 501, high leakage occurs between the upper and lower word lines, resulting in the problem of reliability of the device.